Arsenic high solid solubility, high atomic mass, and limited TED makes it appealing as n-type dopant for shallow junctions of advanced CMOS technology. However, it is well known that thermal treatments in the range of 600-800 °C can electrically de-activate As even at concentrations lower than solid solubility. Laser sub-melt annealing (LA) is an important process for advanced technology nodes since it can deliver very high level of electrical activation together with no diffusion. Integration of the LA in chip fabrication process flow however requires a good understanding of the process parameters to produce stable As distributions and avoid As de-activation. In this work, multi-layer structures consisting of 10 nm thick B doped layers (5E18 at/cm3) separated by 50 nm thick Si spacers were implanted (1e15 at/cm2, 2keV) with As or Ge. The thin B layers can be used as self-interstitial detectors when As is electrically de-activated [1]. Ge implants are expected to produce similar Si lattice damage like As, thus can identify the contribution of point defects related to end-of-range defect formation/dissolution. After LA at 1100°C or 1300°C, samples were annealed at 700°C for 1-30 minutes to induce As de-activation, and analyzed by SIMS, TEM, and EXAFS spectroscopy. Results based on the experimentally observed B diffusion for different LA will be discussed. [1] Rousseau et al., JAP 84(7), 1998, 3593
Observation of Point defect injection from electrical de-activation of Arsenic ultra-shallow distributions formed by ultra-low energy ion implantation and laser sub-melt annealing
Demenev, Evgeny;Meirer, Florian;Giubertoni, Damiano;Pepponi, Giancarlo;Gennaro, Salvatore;Bersani, Massimo;
2013-01-01
Abstract
Arsenic high solid solubility, high atomic mass, and limited TED makes it appealing as n-type dopant for shallow junctions of advanced CMOS technology. However, it is well known that thermal treatments in the range of 600-800 °C can electrically de-activate As even at concentrations lower than solid solubility. Laser sub-melt annealing (LA) is an important process for advanced technology nodes since it can deliver very high level of electrical activation together with no diffusion. Integration of the LA in chip fabrication process flow however requires a good understanding of the process parameters to produce stable As distributions and avoid As de-activation. In this work, multi-layer structures consisting of 10 nm thick B doped layers (5E18 at/cm3) separated by 50 nm thick Si spacers were implanted (1e15 at/cm2, 2keV) with As or Ge. The thin B layers can be used as self-interstitial detectors when As is electrically de-activated [1]. Ge implants are expected to produce similar Si lattice damage like As, thus can identify the contribution of point defects related to end-of-range defect formation/dissolution. After LA at 1100°C or 1300°C, samples were annealed at 700°C for 1-30 minutes to induce As de-activation, and analyzed by SIMS, TEM, and EXAFS spectroscopy. Results based on the experimentally observed B diffusion for different LA will be discussed. [1] Rousseau et al., JAP 84(7), 1998, 3593I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
