For CMOS technology, generations beyond the 65 nm node a major goal is achieving highly activated, ultra-shallow and abrupt profiles. In the case of p-type (boron) implants, one method to achieve this is using Ge preamorphization (PAI) prior to ultra-low energy B implantation. However, for future technology nodes, new issues arise when bulk silicon is supplanted by silicon-on-insulator (SOI). Understanding the strong impact of the buried Si/SiO2 interface, will enable tests of fundamental models on defect evolution, electrical activation and diffusion. In the present study, boron has been implanted in germanium-preamorphized silicon and SOI wafers. Subsequent to implantation, an isochronal and isothermal annealing study of the samples was carried out. Electrical and structural properties were measured by Hall effect and SIMS techniques. The results show a range of effects in both substrate types, including TED and deactivation driven by interstitials from the end-of-range (EOR) defects. However, in the SOI material there is a lower boron deactivation and the EOR defects are eliminated at a lower thermal budget in SOI than in the bulk silicon due to competition between the upper SOI interface and the Si surface which both act as sinks for interstitials.

Understanding the role of buried Si/SiO2 interface on dopant and defect evolution in PAI USJ

Bersani, Massimo;Giubertoni, Damiano;
2005

Abstract

For CMOS technology, generations beyond the 65 nm node a major goal is achieving highly activated, ultra-shallow and abrupt profiles. In the case of p-type (boron) implants, one method to achieve this is using Ge preamorphization (PAI) prior to ultra-low energy B implantation. However, for future technology nodes, new issues arise when bulk silicon is supplanted by silicon-on-insulator (SOI). Understanding the strong impact of the buried Si/SiO2 interface, will enable tests of fundamental models on defect evolution, electrical activation and diffusion. In the present study, boron has been implanted in germanium-preamorphized silicon and SOI wafers. Subsequent to implantation, an isochronal and isothermal annealing study of the samples was carried out. Electrical and structural properties were measured by Hall effect and SIMS techniques. The results show a range of effects in both substrate types, including TED and deactivation driven by interstitials from the end-of-range (EOR) defects. However, in the SOI material there is a lower boron deactivation and the EOR defects are eliminated at a lower thermal budget in SOI than in the bulk silicon due to competition between the upper SOI interface and the Si surface which both act as sinks for interstitials.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11582/3798
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