Design of low power preamplifier IC for cochlear implant using split folded cascode technique

According to the WHO (World Health Organization) report, out of 360 million people, i.e. over 5% of world population, have a disabling hearing loss. Designing a low-cost cochlear implant for hearing aid device is therefore of great importance. The overall cochlear system consists of several blocks, namely, the microphone for sensing the sound waves, the preamplifier for boosting the signal level and the signal processing unit to generate electrical pulses for the electrode to stimulate the auditory nerve. In this paper, we address the design of the High-gain Low Power Preamplifier block for cochlear implants, as it plays a crucial role for the incoming signal to be further processed. In particular, a new technique named Split Folded Cascode (SFC) for designing the Operational Transconductance Amplifier (OTA) is proposed. This arrangement enhances the performance of normal cascode solutions. This technique splits the current in two different branches and increases the overall transconductance by 1.414 times. Simulations and post layout analysis have been carried out for the proposed preamplifier in Cadence Virtuoso using Semi-Conductor Laboratory (SCL) 180 nm technology parameters. In this proposed design a mid-band gain of 43.7 dB, bandwidth of 18–20 kHz and noise 473.47 nV/√Hz at 4 kHz are obtained.