A 128 times 64 pixel programmable vision sensor performs real-time analog image processing over high dynamic range images is reported. The pixel-parallel single instruction multiple data (SIMD) architecture executes real-time spatio-temporal filtering with 2.8 GOPS/mm2 and large flexibility in coefficient assignment. The sensor uses time-based and pulse-based operating modalities to execute spatio-temporal filtering on images with dynamic range up to about 100 dB. The in-pixel processing is based on two operations: the absolute value of voltage difference and accumulation of partial results. Feature extraction from the entire image is also possible without the need for image dispatching, thus optimizing both processing speed and video bandwidth. The 32.6 mum square pixel, with a fill-factor of 24%, consists of two analog memories and 28 transistors. The sensor, fabricated in 0.35 mum CMOS technology, gives a fixed pattern noise (FPN) of 0.8% and power consumption of 14 mW at 3.3 V.

A 100 dB Dynamic-Range CMOS Vision Sensor With Programmable Image Processing and Global Feature Extraction

Massari, Nicola;Gottardi, Massimo
2007

Abstract

A 128 times 64 pixel programmable vision sensor performs real-time analog image processing over high dynamic range images is reported. The pixel-parallel single instruction multiple data (SIMD) architecture executes real-time spatio-temporal filtering with 2.8 GOPS/mm2 and large flexibility in coefficient assignment. The sensor uses time-based and pulse-based operating modalities to execute spatio-temporal filtering on images with dynamic range up to about 100 dB. The in-pixel processing is based on two operations: the absolute value of voltage difference and accumulation of partial results. Feature extraction from the entire image is also possible without the need for image dispatching, thus optimizing both processing speed and video bandwidth. The 32.6 mum square pixel, with a fill-factor of 24%, consists of two analog memories and 28 transistors. The sensor, fabricated in 0.35 mum CMOS technology, gives a fixed pattern noise (FPN) of 0.8% and power consumption of 14 mW at 3.3 V.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11582/8073
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