A prototype of a mixed-mode ASIC composed of a fast readout architecture that interfaces with a matrix of 4096 Monolithic Active Pixel Sensor (MAPS) was fabricated via STM 130 nm CMOS technology. Groups of 4×4 pixels form a macro-pixel (MP). The readout architecture is parallel and could overcome the readout speed limit of big matrices. As the output port can only accept one-hit information at a time, an internal queuing system has been provided to face high hit-rate conditions. The ASIC can work in two different manners as it can be connected to an actual full-custom matrix of MAPS or to a digital matrix emulator composed of standard cells, for testing facilities. For both operating modes a slow-control phase is required to load the chip configuration. Previous versions of similar ASICs were designed and tested. The work is aimed at improving the design of MAPS detectors with an on-chip fast sparsification system, for particle tracking, to match the requirements of future high-energy physics experiments. The readout architecture implemented is data driven extending the flexibility of the system to be also used in first level triggers on tracks in vertex detectors. Preliminary simulations and tests indicate that the readout system can cope with an average hit-rate up to 100 MHz/cm2 if a master clock of 80 MHz is used, while maintaining an overall efficiency over 99%.

A 4096-pixel MAPS device with on-chip data sparsification

Giacomini, Gabriele;Dalla Betta, Gian Franco;Soncini, Giovanni;Pancheri, Lucio;
2009

Abstract

A prototype of a mixed-mode ASIC composed of a fast readout architecture that interfaces with a matrix of 4096 Monolithic Active Pixel Sensor (MAPS) was fabricated via STM 130 nm CMOS technology. Groups of 4×4 pixels form a macro-pixel (MP). The readout architecture is parallel and could overcome the readout speed limit of big matrices. As the output port can only accept one-hit information at a time, an internal queuing system has been provided to face high hit-rate conditions. The ASIC can work in two different manners as it can be connected to an actual full-custom matrix of MAPS or to a digital matrix emulator composed of standard cells, for testing facilities. For both operating modes a slow-control phase is required to load the chip configuration. Previous versions of similar ASICs were designed and tested. The work is aimed at improving the design of MAPS detectors with an on-chip fast sparsification system, for particle tracking, to match the requirements of future high-energy physics experiments. The readout architecture implemented is data driven extending the flexibility of the system to be also used in first level triggers on tracks in vertex detectors. Preliminary simulations and tests indicate that the readout system can cope with an average hit-rate up to 100 MHz/cm2 if a master clock of 80 MHz is used, while maintaining an overall efficiency over 99%.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11582/54183
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