A new method for conductive via’s using gold electroplating is presented. Tapered walls through wafer via (TWV) holes were made using a variable isotropy DRIE process, with a very good control over the obtained angles – angles of 11.3° and 21.8° were obtained with errors smaller than 10%. Barrier and seed layers were deposited in via’s performed by PVD (Physical Vapor Deposition) techniques with a very good coverage of the walls. Finally, gold electroplating was used to fill the narrow part of via’s.

Fabrication of Through-Wafer Interconnections by Gold Electroplating

Vasilache, Dan Adrian;Colpo, Sabrina;Giacomozzi, Flavio;Margesin, Benno;Chistè, Matteo
2011

Abstract

A new method for conductive via’s using gold electroplating is presented. Tapered walls through wafer via (TWV) holes were made using a variable isotropy DRIE process, with a very good control over the obtained angles – angles of 11.3° and 21.8° were obtained with errors smaller than 10%. Barrier and seed layers were deposited in via’s performed by PVD (Physical Vapor Deposition) techniques with a very good coverage of the walls. Finally, gold electroplating was used to fill the narrow part of via’s.
978-1-61284-171-7
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11582/49808
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