Chistè, Matteo
Chistè, Matteo
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Risultati 1 - 5 di 5 (tempo di esecuzione: 0.008 secondi).
Conductive through silicon via holes for RF applications
2012-01-01 Vasilache, Dan Adrian; Colpo, Sabrina; Chistè, Matteo; Giacomozzi, Flavio; Margesin, Benno
Fabrication of novel MEMS microgrippers by deep reactive ion etching with metal hard mask
2017-01-01 Bagolini, Alvise; Ronchin, Sabina; Bellutti, Pierluigi; Chistè, Matteo; Verotti, Matteo; Pio Belfiore, Nicola
Fabrication of Through-Wafer Interconnections by Gold Electroplating
2011-01-01 Vasilache, Dan Adrian; Colpo, Sabrina; Giacomozzi, Flavio; Margesin, Benno; Chistè, Matteo
OPTIMIZED DRIE PROCESS FOR TAPERED WALLS THROUGH WAFER VIA HOLES MANUFACTURING
2012-01-01 Vasilache, Dan Adrian; Colpo, Sabrina; Margesin, Benno; Giacomozzi, Flavio; Chistè, Matteo; P., Schiopu
Wafer resistivity influence over DRIE processes for TSVs manufacturing
2012-01-01 Vasilache, Dan Adrian; Chistè, Matteo; Colpo, Sabrina; Giacomozzi, Flavio; Margesin, Benno
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| Conductive through silicon via holes for RF applications | 1-gen-2012 | Vasilache, Dan Adrian; Colpo, Sabrina; Chistè, Matteo; Giacomozzi, Flavio; Margesin, Benno | |
| Fabrication of novel MEMS microgrippers by deep reactive ion etching with metal hard mask | 1-gen-2017 | Bagolini, Alvise; Ronchin, Sabina; Bellutti, Pierluigi; Chistè, Matteo; Verotti, Matteo; Pio Belfiore, Nicola | |
| Fabrication of Through-Wafer Interconnections by Gold Electroplating | 1-gen-2011 | Vasilache, Dan Adrian; Colpo, Sabrina; Giacomozzi, Flavio; Margesin, Benno; Chistè, Matteo | |
| OPTIMIZED DRIE PROCESS FOR TAPERED WALLS THROUGH WAFER VIA HOLES MANUFACTURING | 1-gen-2012 | Vasilache, Dan Adrian; Colpo, Sabrina; Margesin, Benno; Giacomozzi, Flavio; Chistè, Matteo; P., Schiopu | |
| Wafer resistivity influence over DRIE processes for TSVs manufacturing | 1-gen-2012 | Vasilache, Dan Adrian; Chistè, Matteo; Colpo, Sabrina; Giacomozzi, Flavio; Margesin, Benno |