This paper presents the results of edge-Transient Current Technique (e-TCT) measurements of a test structure of a High Voltage CMOS (HV-CMOS) pixel demonstrator, the H35DEMO. Several high resistivity (1000 cm) samples of the device were thinned to 100, processed for backside biasing, and irradiated with neutrons to fluences up to ncm−2. The evolution of effective doping concentration with respect to fluence is studied. Samples irradiated to a fluence of ncm−2 are fully depleted beyond V substrate bias voltage while samples irradiated to the highest fluence reach 30 m depletion at V.
E-TCT characterization of a thinned, backside biased, irradiated HV-CMOS pixel test structure
M. Franks
;G. Casse;
2021-01-01
Abstract
This paper presents the results of edge-Transient Current Technique (e-TCT) measurements of a test structure of a High Voltage CMOS (HV-CMOS) pixel demonstrator, the H35DEMO. Several high resistivity (1000 cm) samples of the device were thinned to 100, processed for backside biasing, and irradiated with neutrons to fluences up to ncm−2. The evolution of effective doping concentration with respect to fluence is studied. Samples irradiated to a fluence of ncm−2 are fully depleted beyond V substrate bias voltage while samples irradiated to the highest fluence reach 30 m depletion at V.File in questo prodotto:
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