In this article, we show that a p-channel silicon Junction Field Effect Transistor (JFET) can be obtained within a conventional CMOS n-well technology with no additional process steps but a simple layout modification of the p-channel-stop mask; in fact, in the suggested technology, the p-channel of the JFET is obtained by using the same CMOS p-stop implantation step. Results from the electrical characterization of a specially designed test-chip confirmed the validity of the device concept and its full compatibility with CMOS devices; in particular, JFETs exhibit high transconductance and output resistance as well as low gate current and input capacitance. The proposed technological approach has therefore proved to be suitable for the realization of p-JFET–CMOS low-noise circuits.
An all-implanted p-channel Si JFET fully compatible with CMOS technology
Dalla Betta, Gian Franco;Bellutti, Pierluigi;Boscardin, Maurizio;Ferrario, Lorenza;Soncini, Giovanni;Zorzi, Nicola
1999-01-01
Abstract
In this article, we show that a p-channel silicon Junction Field Effect Transistor (JFET) can be obtained within a conventional CMOS n-well technology with no additional process steps but a simple layout modification of the p-channel-stop mask; in fact, in the suggested technology, the p-channel of the JFET is obtained by using the same CMOS p-stop implantation step. Results from the electrical characterization of a specially designed test-chip confirmed the validity of the device concept and its full compatibility with CMOS devices; in particular, JFETs exhibit high transconductance and output resistance as well as low gate current and input capacitance. The proposed technological approach has therefore proved to be suitable for the realization of p-JFET–CMOS low-noise circuits.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
