We propose a novel n–p–n BJT radiation detector on high-resistivity silicon with integrated p–n–p transistor providing the quiescent base current of the detector. The dc operational limits of the proposed detector are analysed by means of numerical device simulations, pointing out that, by properly distancing the base of the p–n–p transistor from the emitter of the n–p–n detector, the latch-up of the parasitic thyristor embedded within the detector-plus-biasing-transistor structure takes place at relatively high current levels, where detector operation should anyway be avoided in order to prevent the associated current-gain loss. Numerical simulations provides insight about the bias dependence of charge-collection waveforms, indicating that minimization of the collecting time requires the detector quiescent current to be adjusted at the highest value still allowing high-injection effects to be avoided. A small-signal equivalent circuit of the proposed structure is also derived, allowing the impact of p–n–p biasing transistor and load resistance on the charge-collecting time constant to be evaluated. First experimental results show that fabricated structures are immune from the latch-up of the parasitic thyristor throughout their high-current-gain operating region and feature a minimum charge-collecting time constant of 35 µs, as tested by pulsed laser illumination.

N–p–n bipolar-junction-transistor detector with integrated p–n–p biasing transistor — feasibility study, design and first experimental results

Piemonte, Claudio;Boscardin, Maurizio;
2006

Abstract

We propose a novel n–p–n BJT radiation detector on high-resistivity silicon with integrated p–n–p transistor providing the quiescent base current of the detector. The dc operational limits of the proposed detector are analysed by means of numerical device simulations, pointing out that, by properly distancing the base of the p–n–p transistor from the emitter of the n–p–n detector, the latch-up of the parasitic thyristor embedded within the detector-plus-biasing-transistor structure takes place at relatively high current levels, where detector operation should anyway be avoided in order to prevent the associated current-gain loss. Numerical simulations provides insight about the bias dependence of charge-collection waveforms, indicating that minimization of the collecting time requires the detector quiescent current to be adjusted at the highest value still allowing high-injection effects to be avoided. A small-signal equivalent circuit of the proposed structure is also derived, allowing the impact of p–n–p biasing transistor and load resistance on the charge-collecting time constant to be evaluated. First experimental results show that fabricated structures are immune from the latch-up of the parasitic thyristor throughout their high-current-gain operating region and feature a minimum charge-collecting time constant of 35 µs, as tested by pulsed laser illumination.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11582/31412
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