This paper presents the performance of a MEMS zero-level chip cap package implemented with through-the-cap vertical interconnects. The interconnect as well as the hermetic bond and sealing are established using flip-chip thermo-compression bonding by creating a copper-tin to gold metallic (solder) joint. The hermeticity of the packages is assessed via electrical measurements of encapsulated MEMS resonators and the RF performance of 3D interconnects is evaluated via microwave measurements of integrated coplanar waveguides. Design guidelines imposed by concurrent requirements of the flip-chip assembly process and the RF performance are discussed. The developed technology for the MEMS cap uses CMOS-compatible materials and the CMOS fabrication process.
Performance and Perspectives of Zero-Level MEMS Chip Packages with Vertical Interconnects
Faes, Alessandro;Margesin, Benno;
2014-01-01
Abstract
This paper presents the performance of a MEMS zero-level chip cap package implemented with through-the-cap vertical interconnects. The interconnect as well as the hermetic bond and sealing are established using flip-chip thermo-compression bonding by creating a copper-tin to gold metallic (solder) joint. The hermeticity of the packages is assessed via electrical measurements of encapsulated MEMS resonators and the RF performance of 3D interconnects is evaluated via microwave measurements of integrated coplanar waveguides. Design guidelines imposed by concurrent requirements of the flip-chip assembly process and the RF performance are discussed. The developed technology for the MEMS cap uses CMOS-compatible materials and the CMOS fabrication process.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
