The TOTEM neurochip has proved its variability as a system for real time computation in HEP and space applications requiring high performance for event classification, data mining, and signal processing. ISA and VME boards integrating the TOTEM chip as a coprocessor have been made available to selected experimental groups which reported satisfactory results. This paper presents a new architectural solution yielding higher performance and reduced silicon area. The on-chip computational structures have been entirely redesigned to take advantage of a novel approach to number representation that, at the cost of a provably-bounded approximation, leads to a much-reduced silicon area, lower power dissipation, and faster computation. This approach is validated by simulation results on experimental data, as presented in the paper
Advances in the Design of the TOTEM Neurochip
1996-01-01
Abstract
The TOTEM neurochip has proved its variability as a system for real time computation in HEP and space applications requiring high performance for event classification, data mining, and signal processing. ISA and VME boards integrating the TOTEM chip as a coprocessor have been made available to selected experimental groups which reported satisfactory results. This paper presents a new architectural solution yielding higher performance and reduced silicon area. The on-chip computational structures have been entirely redesigned to take advantage of a novel approach to number representation that, at the cost of a provably-bounded approximation, leads to a much-reduced silicon area, lower power dissipation, and faster computation. This approach is validated by simulation results on experimental data, as presented in the paperI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
