This paper presents for the first time influence of the silicon resistivity over the DRIE processes. Our aim was to develop a new process for tapered walls through silicon vias (TSVs) with a good control over the walls angle. Different wafer types were used and a dependency of resistivity was found, with an important impact over the TSVs shape. Solution found is presented and experiments performed to obtained designed TSVs.

Wafer resistivity influence over DRIE processes for TSVs manufacturing

Vasilache, Dan Adrian;Chistè, Matteo;Colpo, Sabrina;Giacomozzi, Flavio;Margesin, Benno
2012

Abstract

This paper presents for the first time influence of the silicon resistivity over the DRIE processes. Our aim was to develop a new process for tapered walls through silicon vias (TSVs) with a good control over the walls angle. Different wafer types were used and a dependency of resistivity was found, with an important impact over the TSVs shape. Solution found is presented and experiments performed to obtained designed TSVs.
9781467307369
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11582/122601
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