Monolithic Active Pixel Sensors (MAPS) are increasingly employed in high-energy physics experiments due to their low power consumption, excellent spatial resolution, and fully digital readout. Forthcoming upgrades at CERN will adopt MAPS fabricated using advanced CMOS nodes, transitioning from 180 nm to 65 nm. This shift enables significantly higher digital data rates, exceeding 1.2, Gbps, and supports improved time resolution and detector granularity. However, the integration of such high-speed devices with PCBs introduces substantial challenges, including signal degradation, impedance mismatches, and increased power losses. Standard PCBbased interconnects are generally incompatible with the stringent requirements of inner tracking systems, particularly in terms of thickness and the need for materials with low radiation length X0, commonly referred to as the material budget. To address these limitations, we are developing a wafer-level packaging strategy based on ultra-thin, flexible Kapton-aluminum substrates. This approach combines photolithographic patterning, wet and dry etching, and singlepoint Tape Automated Bonding (spTAB). This work presents the complete process chain, from material selection and fabrication to interconnect formation and characterization. Emphasis is placed on achieving signal integrity and minimizing material budget to meet the demands of nextgeneration MAPS-based detectors operating in high-rate, high-radiation environments.
R&D on Flexible and Low-Material-Budget Packaging for High-Frequency Communication in Future MAPS Detectors
Novel, D.
;Lega, A.;Facchinelli, T.;Bellutti, P.
2025-01-01
Abstract
Monolithic Active Pixel Sensors (MAPS) are increasingly employed in high-energy physics experiments due to their low power consumption, excellent spatial resolution, and fully digital readout. Forthcoming upgrades at CERN will adopt MAPS fabricated using advanced CMOS nodes, transitioning from 180 nm to 65 nm. This shift enables significantly higher digital data rates, exceeding 1.2, Gbps, and supports improved time resolution and detector granularity. However, the integration of such high-speed devices with PCBs introduces substantial challenges, including signal degradation, impedance mismatches, and increased power losses. Standard PCBbased interconnects are generally incompatible with the stringent requirements of inner tracking systems, particularly in terms of thickness and the need for materials with low radiation length X0, commonly referred to as the material budget. To address these limitations, we are developing a wafer-level packaging strategy based on ultra-thin, flexible Kapton-aluminum substrates. This approach combines photolithographic patterning, wet and dry etching, and singlepoint Tape Automated Bonding (spTAB). This work presents the complete process chain, from material selection and fabrication to interconnect formation and characterization. Emphasis is placed on achieving signal integrity and minimizing material budget to meet the demands of nextgeneration MAPS-based detectors operating in high-rate, high-radiation environments.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
