Design and Simulation of Dual Material Double Gate Junctionless MOSFET (DM-DG-JL-MOSFET) with High-K Gate Stacking

This paper introduces a study focused on the symmetric configuration of the Dual Material Double Gate Junctionless MOSFET (DM-DG-JL-MOSFET). The investigation utilizes TCAD simulation to assess the performance of the DM-DG-JL-MOSFET by examining alterations in key parameters such as drain current, electric field distribution, sub-threshold slope, surface potential, and ION/IOFF ratio. The simulations of the DM-DG-JL-MOSFET encompass various influential factors, including variations in metal work function, structural adjustments related to oxide thickness, and alterations in oxide material composition. The device architecture proposed in this research showcases promising outcomes, underscoring the superior efficiency of the DM-DG Stack MOSFET.