A shared well 4x4 SPAD array test structure with 3μm pitch is realized in a 130nm CMOS image sensor technology. The SPADs have 150Hz median DCR at room temperature at 1V excess bias, 15% peak PDP and 176ps FWHM timing jitter both at 3V excess bias.
3μm Pitch, 1μm Active Diameter SPAD Arrays in 130nm CMOS Imaging Technology
Luca Parmesan;
2017-01-01
Abstract
A shared well 4x4 SPAD array test structure with 3μm pitch is realized in a 130nm CMOS image sensor technology. The SPADs have 150Hz median DCR at room temperature at 1V excess bias, 15% peak PDP and 176ps FWHM timing jitter both at 3V excess bias.File in questo prodotto:
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