Single Event Upset tests for a CMOS 0.35μ front-end and readout electronics for high-flux particle detectors

The Single Event Upset rate of a 64 channels integrated circuit, designed in CMOS $0.35 μm technology, has been measured and analyzed at the SIRAD facility of the Italian National Institute for Nuclear Physics (INFN). The chip, named TERA09, is a current to frequency converter designed to readout monitor chambers in particle therapy. In this field, the accelerator development is moving toward compact solutions providing high-intensity pulsed-beams. The TERA09 chip is capable to operate in a wide input current range, from few nA to hundreds of μA, with linearity deviations in the order of few percent. The chip is designed to be located aside of the monitoring chambers, far from the therapeutic beam, and no protection from data corruption from single events was implemented in its design. However, considering the relatively large area of the chip covered by data registers and the secondary neutrons field produced during the irradiation, the potential exposure to data corruption by Single Event Effect phenomena need to be addressed. The aim of the tests at SIRAD is to study the upset rate as a function of the energy deposited by single events by irradiating the chip with ions of different LET. From the analysis of the data it is possible to predict the single event effect cross-section in a clinical environment and estimate the readout failure probability in a real application scenario.