This paper reports on a Q VGA vision sensor embedding 160 column-level digital processors executing real-time tunable scene background subtraction for robust event detection. The single-ramp column-parallel ADCs are used to estimate the pixel variations and detecting anomalous behaviors against two reference images stored in on-chip. The sensor generates a 160×120 pixel bitmap associated to potential alert conditions. The chip is powered at 3.3V/1.2V for the analog/digital parts and consumes 1.6mW when operating at 15fps dispatching gray-scale image and a quarter QVGA bitmap.

A 1.6 mW 320×240-pixel vision sensor with programmable dynamic background rejection and motion detection

Zou, Yu
;
Gottardi, M.;Perenzoni, Daniele;Perenzoni, M.;Stoppa, D.
2017

Abstract

This paper reports on a Q VGA vision sensor embedding 160 column-level digital processors executing real-time tunable scene background subtraction for robust event detection. The single-ramp column-parallel ADCs are used to estimate the pixel variations and detecting anomalous behaviors against two reference images stored in on-chip. The sensor generates a 160×120 pixel bitmap associated to potential alert conditions. The chip is powered at 3.3V/1.2V for the analog/digital parts and consumes 1.6mW when operating at 15fps dispatching gray-scale image and a quarter QVGA bitmap.
978-1-5090-1012-7
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11582/312890
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