Process simulations of a fabrication technology for detector compatible front-end circuits on high-resistivity silicon

This report describes the activity carried out to characterize, by means of a process simulator, a technology (developed at ITC-irst in 1999) aimed at the production of particle detectors with integrated front-end electronics. The main part of the work has been dedicated to the calibration of the parameters involved in the simu- lation of the implantation and diffusion steps. This has been carried out comparing the calculated dopant profiles with a set of experimental data (SIMS, Spreading Resistance, Capacitance-Voltage measurements). It has been evidenced that it is extremely important to have dierent types of measurement for each layer in order to obtain an accurate calibration. In general, satisfactory results have been achived, and the simulated profiles can now be used to perform device simulations of the transistors implemented in the layout. Furthermore, a calibrated process simulator allows the definition of a new process flow with improved characteristics