A new architecture for Positron Emission Tomography visible-light detectors is presented. The architecture is based on mini-SiPMs (arrays of 32 SPADs), which are locally digitized. With this architecture we expect to achieve a high fill factor while still performing an early enough analog-to-digital conversion so as to avoid interconnect parasitics common of standard SiPMs. The detector is implemented as a 14 × 10 pixel array where each pixel contains a mini-SiPM, a digital counter and individual SPAD SRAMs for disabling high DCR devices. The achieved fill factor is 29% and the expected maximum event rate is 16 kcps.
A mini-SiPM array for PET detectors implemented in a 0.35-um HV CMOS technology
Huf Campos Braga, Leo;Pancheri, Lucio;Gasparini, Leonardo;Stoppa, David
2011-01-01
Abstract
A new architecture for Positron Emission Tomography visible-light detectors is presented. The architecture is based on mini-SiPMs (arrays of 32 SPADs), which are locally digitized. With this architecture we expect to achieve a high fill factor while still performing an early enough analog-to-digital conversion so as to avoid interconnect parasitics common of standard SiPMs. The detector is implemented as a 14 × 10 pixel array where each pixel contains a mini-SiPM, a digital counter and individual SPAD SRAMs for disabling high DCR devices. The achieved fill factor is 29% and the expected maximum event rate is 16 kcps.File in questo prodotto:
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