Sub-100 ps LSB Time-to-Digital Converter with Voltage- or Current-Based Resolution Control

This paper describes the design of a sub-100 ps resolution Time-to-Digital Converter equipped with a time resolution control system. A controlled-voltage (CV) and a controlled-current (CC) approaches are proposed and compared. The key performance parameters, including timing resolution, dynamic power consumption, linearity, and jitter, are evaluated as a compromise with the system size. Simulations indicate that, in nominal conditions, the CV solution exhibits a power consumption of 2.2 mW and a resolution of 64 ps, while the CC method achieves a power consumption of 0.92 mW while maintaining a resolution of 80 ps.