Interconnect Simulation Using Padé Approximation for Image Sensors

A lightweight simulator for on-chip interconnects is presented. The simulator is meant to aid in the optimization of interconnect circuits in pixel arrays where the timing of signals is crucial. The simulator implements an implicit integration scheme and takes advantage of the Padé approximation of the interconnect impedance. Moreover, transistors are treated according to the n-th power model, which is compact and efficient. The performance of the proposed simulator is compared with SPICE in a 110 nm standard CMOS technology, achieving a relative error smaller than 11.3 % in propagation delay estimates.