A test structure comprehending an antenna-coupled FET-based THz detector integrated with readout electronics is designed and fabricated in a 0.15-μm standard CMOS technology. A low-noise preamplification technique has been employed, based on parametric chopper amplifier, substituting the lock-in apparatus and performing direct analog-to-digital conversion by means of an incremental ΣΔ converter. The input-referred noise of 1.6 μVrms is such that the Noise Equivalent Power (NEP) of the FET detector is not degraded. The measured signal-to-noise ratio (SNR) is 65 dB which is equivalent to 10.6 effective number of bits (ENOB). The readout chain area is 90 × 300 μm2. The measured power consumption is 80 μW from 1.8 V supply.
A CMOS 0.15-μm in-pixel noise reduction technique for readout of antenna-coupled FET-based THz detectors
Moustafa Khatib
2016-01-01
Abstract
A test structure comprehending an antenna-coupled FET-based THz detector integrated with readout electronics is designed and fabricated in a 0.15-μm standard CMOS technology. A low-noise preamplification technique has been employed, based on parametric chopper amplifier, substituting the lock-in apparatus and performing direct analog-to-digital conversion by means of an incremental ΣΔ converter. The input-referred noise of 1.6 μVrms is such that the Noise Equivalent Power (NEP) of the FET detector is not degraded. The measured signal-to-noise ratio (SNR) is 65 dB which is equivalent to 10.6 effective number of bits (ENOB). The readout chain area is 90 × 300 μm2. The measured power consumption is 80 μW from 1.8 V supply.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
