A comparison of FPGA architectures to extract gamma arrival times from multiple-timestamp digital SiPM PET detectors

Recently proposed Digital Silicon Photo-Multipliers integrate arrays of Time-to-Digital Converters thus providing multiple photon timestamps for each detected gamma. A considerable amount of data is generated and has to be processed to estimate the actual time of arrival of the gamma. This is typically performed on the FPGA present on the controller board. The processing stages include: (i) back conversion from TDC code to time, (ii) sorting, (iii) finding the timestamp of the first scintillation photon, removing noisy events (dark counts), (iv) and final processing to extract the Time of Arrival. In this work we discuss the implementation of two architectures specifically designed for this purpose and analyze their impact in terms of device utilization and timing. The architectures have been tested with the data generated by the SPADnet-I sensor, a 8×16-pixel d-SiPM, that generates up to 256 photon timestamps for every detected gamma.