In RF-MEMS packaging, next to the protection of movable parts from the harmful environment, key factor is also optimization of the package electrical performance. In this work the process degrees of freedom (dofs) of a specific wafer-level packaging process are investigated in order to minimize its electrical parasitic effects introduced mainly by a capping silicon substrate containing through-substrate electrical interconnect and Isotropic/Anisotropic Conductive Adhesive. The optimization is performed with the Ansoft HFSS electromagnetic simulator. The simulations results show that the optimum is reached by adopting an high-resistivity silicon substrate for the capping part and that its thickness must be around 250 μm. Moreover, the recess depth and the spacing in between the two wafers are optimized in order to reduce the influence of the capping part on the RF behaviour of MEMS devices. In addition, possible packaging solutions including a hermetic sealing ring and the integration with the CMOS part (hybrid-packaging) are discussed. The influence of the sealing rings (electrically floating or grounded) on the RF-behaviour of MEMS devices is presented.

Electrical Optimization of a Wafer-Level Package for RF-MEMS Applications

Iannacci, Jacopo;
2006

Abstract

In RF-MEMS packaging, next to the protection of movable parts from the harmful environment, key factor is also optimization of the package electrical performance. In this work the process degrees of freedom (dofs) of a specific wafer-level packaging process are investigated in order to minimize its electrical parasitic effects introduced mainly by a capping silicon substrate containing through-substrate electrical interconnect and Isotropic/Anisotropic Conductive Adhesive. The optimization is performed with the Ansoft HFSS electromagnetic simulator. The simulations results show that the optimum is reached by adopting an high-resistivity silicon substrate for the capping part and that its thickness must be around 250 μm. Moreover, the recess depth and the spacing in between the two wafers are optimized in order to reduce the influence of the capping part on the RF behaviour of MEMS devices. In addition, possible packaging solutions including a hermetic sealing ring and the integration with the CMOS part (hybrid-packaging) are discussed. The influence of the sealing rings (electrically floating or grounded) on the RF-behaviour of MEMS devices is presented.
961-91023-5-5
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11582/300109
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