Electrical Performance Assessment and Optimization of an RF MEMS Wafer Level Package

In this work, a wafer-level packaging solution for RF-MEMS applications that is based on a capping silicon substrate is presented. The electrical signals redistribution from the device wafer to the capping one is provided by vertical through-wafer etched vias filled with copper. The bonding of the capping part to the device substrate is performed at wafer-level using electrically conductive adhesives (ECA) or solder-bump reflow. Moreover, an extensive electromagnetic optimization is performed in order to assess and minimize the additional losses (capacitive and inductive couplings) introduced by the application of the package. To this purpose, the influence of all technology degrees of freedom (DoFs) on the RF-performances of capped devices are investigated using Ansoft HFSS. Furthermore, test structures (transmission lines and shorts) have been fabricated and packaged. Comparison of experimental and simulated data for the capped and uncapped structures is presented.