We report on the main design and technological issues related to a modified 3D-DTTC (Double-side, Double-Type-Column) detector process at FBK (Trento, Italy). With respect to the previous versions of this technology, which involved columnar electrodes of both doping types etched from both wafer sides and stopping at a short distance from the opposite surface, passing-through columns are now available. This is expected to enhance the performance but most of all to make it more reproducible, having in mind medium volume productions. An additional benefit is the feasibility of slim edges, which consist of a multiple ohmic column termination with an overall size in the order of 200 μm. Two batches of detectors have been fabricated at FBK using this modified 3D-DDTC approach, and with two different wafer layouts including several design options, among them the ATLAS 3D sensor prototypes compatible with the new read-out chip FE-I4. Selected results from the characterization of test structures from the first processed wafer are reported.
Development of Modified 3D Detectors at FBK
Bagolini, Alvise;Boscardin, Maurizio;Gabos, Paolo;Giacomini, Gabriele;Piemonte, Claudio;Povoli, Marco;Vianello, Elisa;Zorzi, Nicola
2010-01-01
Abstract
We report on the main design and technological issues related to a modified 3D-DTTC (Double-side, Double-Type-Column) detector process at FBK (Trento, Italy). With respect to the previous versions of this technology, which involved columnar electrodes of both doping types etched from both wafer sides and stopping at a short distance from the opposite surface, passing-through columns are now available. This is expected to enhance the performance but most of all to make it more reproducible, having in mind medium volume productions. An additional benefit is the feasibility of slim edges, which consist of a multiple ohmic column termination with an overall size in the order of 200 μm. Two batches of detectors have been fabricated at FBK using this modified 3D-DDTC approach, and with two different wafer layouts including several design options, among them the ATLAS 3D sensor prototypes compatible with the new read-out chip FE-I4. Selected results from the characterization of test structures from the first processed wafer are reported.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
