This paper reports the characterization and test of an embedded implementation of the k-Nearest Neighbor (kNN) classifier in a resource constrained device applied to a seat to capture user postures and combine them with contextual information about the user. The embedded platform is a wearable multi-sensor device based on the 32 bit ARM Cortex M3 architecture, capable of data processing (sampling, windowing, filtering, Fast Fourier Transform) from 9 different sensors. The system, applied to the seat, identifies 6 different user postures - adopted while she/he is working on the desk - and fuses the result with the information available from other sensors worn by the user, collecting information about her/his activities and physiological state. The kNN classifier is evaluated in terms of required computational power and latency. 7 users have been monitored along 3 days. The posture recognition accuracy reaches 93.7%, it requires 9KB of memory and introduces a latency of 950usec, satisfying strict real-time requirements.

A context-aware smart seat

Farella, Elisabetta;
2011

Abstract

This paper reports the characterization and test of an embedded implementation of the k-Nearest Neighbor (kNN) classifier in a resource constrained device applied to a seat to capture user postures and combine them with contextual information about the user. The embedded platform is a wearable multi-sensor device based on the 32 bit ARM Cortex M3 architecture, capable of data processing (sampling, windowing, filtering, Fast Fourier Transform) from 9 different sensors. The system, applied to the seat, identifies 6 different user postures - adopted while she/he is working on the desk - and fuses the result with the information available from other sensors worn by the user, collecting information about her/his activities and physiological state. The kNN classifier is evaluated in terms of required computational power and latency. 7 users have been monitored along 3 days. The posture recognition accuracy reaches 93.7%, it requires 9KB of memory and introduces a latency of 950usec, satisfying strict real-time requirements.
978-1-4577-0622-6
978-1-4577-0623-3
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11582/215920
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