In this paper, we use the SPADnet-I sensor, a fully digital 8×16 SiPM array with per-SPAD SRAMs, to analyze the effects photon detection efficiency (PDE), dark count rate (DCR) and saturation on the energy resolution of PET systems. We show that the mini-SiPM compression schemes of SPADnet-I result in a total photon loss of about 6% for a 511 keV gamma LYSO scintillation. The behavior of the sensor energy resolution with respect to variations in PDE and DCR is measured and modeled. The optimum operation point is found to be at circa 8% of the high-DCR SPADs disabled, resulting in 10.9% energy resolution. Moreover, from the described model, we show that integrating per-SPAD SRAMs on-chip actually has a negative effect in the sensor energy resolution due to the reduced fill-factor. Finally, we show that below a certain level of DCR, the optimum operation point shifts to 100% of the SPADs enabled, completely eliminating any gains from integrating per-SPAD SRAMs.

Effects of DCR, PDE and saturation on the energy resolution of digital SiPMs for PET

Huf Campos Braga, Leo;Perenzoni, Matteo;Stoppa, David
2013

Abstract

In this paper, we use the SPADnet-I sensor, a fully digital 8×16 SiPM array with per-SPAD SRAMs, to analyze the effects photon detection efficiency (PDE), dark count rate (DCR) and saturation on the energy resolution of PET systems. We show that the mini-SiPM compression schemes of SPADnet-I result in a total photon loss of about 6% for a 511 keV gamma LYSO scintillation. The behavior of the sensor energy resolution with respect to variations in PDE and DCR is measured and modeled. The optimum operation point is found to be at circa 8% of the high-DCR SPADs disabled, resulting in 10.9% energy resolution. Moreover, from the described model, we show that integrating per-SPAD SRAMs on-chip actually has a negative effect in the sensor energy resolution due to the reduced fill-factor. Finally, we show that below a certain level of DCR, the optimum operation point shifts to 100% of the SPADs enabled, completely eliminating any gains from integrating per-SPAD SRAMs.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11582/185621
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