We report on the design of a new full-analog currend-mode CNN in a 1.2 um CMOS technology, whose cell core is characterized by an intrinsic capability of weights control, low power consumption and small area occupation. Circuit simulations allowed the design approach to be validated and the electrical performance of the CNN to be predicted; moreover, it is shown that the proposed CNN can be successfully adopted for several applications in image processing. A preliminary CNN test-chip, consisting of a 8x1 array for CCD and shadow detection, is currently being fabricated at IRST (Trento, Italy) in a 2.5 um CMOS technology

A new current-mode programmable cellular neural network

Dalla Betta, Gian Franco;
1998

Abstract

We report on the design of a new full-analog currend-mode CNN in a 1.2 um CMOS technology, whose cell core is characterized by an intrinsic capability of weights control, low power consumption and small area occupation. Circuit simulations allowed the design approach to be validated and the electrical performance of the CNN to be predicted; moreover, it is shown that the proposed CNN can be successfully adopted for several applications in image processing. A preliminary CNN test-chip, consisting of a 8x1 array for CCD and shadow detection, is currently being fabricated at IRST (Trento, Italy) in a 2.5 um CMOS technology
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11582/1720
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