In this work we propose a CMOS preamplifier for silicon drift detectors (SDDs) for X-ray spectroscopy as well as gamma-ray imaging applications. As in the case of SiLi and other conventional detectors, the pulsed-reset technique is adopted in this design. In fact, although continuous reset techniques have been employed widely with recent generation of SDDs for spectroscopy mainly thanks to their ease of operation, the additional noise usually introduced by the continuous reset limits the performances especially at high rates or for not-negligible levels of leakage current. This represents a limiting factor especially for the SDD which is especially winning in performances in high-rate conditions. The circuit here presented is a CMOS pulsed-reset preamplifier especially designed for SDDs where the input JFET is integrated on the detector itself. The circuit is suitable for systems using array of SDDs. A single channel circuit has been designed in AMS 0.35 um CMOS technology. The architecture of the circuit and the preliminary results of its experimental characterization are presented in this work.

A CMOS pulsed-reset preamplifier for silicon drift detectors with on-chip JFET

Gola, Alberto Giacomo;
2007

Abstract

In this work we propose a CMOS preamplifier for silicon drift detectors (SDDs) for X-ray spectroscopy as well as gamma-ray imaging applications. As in the case of SiLi and other conventional detectors, the pulsed-reset technique is adopted in this design. In fact, although continuous reset techniques have been employed widely with recent generation of SDDs for spectroscopy mainly thanks to their ease of operation, the additional noise usually introduced by the continuous reset limits the performances especially at high rates or for not-negligible levels of leakage current. This represents a limiting factor especially for the SDD which is especially winning in performances in high-rate conditions. The circuit here presented is a CMOS pulsed-reset preamplifier especially designed for SDDs where the input JFET is integrated on the detector itself. The circuit is suitable for systems using array of SDDs. A single channel circuit has been designed in AMS 0.35 um CMOS technology. The architecture of the circuit and the preliminary results of its experimental characterization are presented in this work.
File in questo prodotto:
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11582/16469
 Attenzione

Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo

Citazioni
  • ???jsp.display-item.citation.pmc??? ND
social impact