This paper presents a hardware solution for the implementation of high-speed control systems based on a neural architecture that, by using a novel number representation, reduces significantly the silicon area required by the realization of the architecture as a digital chip. The neural architecture was originally implemented as the TOTEM neural chip. The new number representation is based on logarithms so that the costly multipliers of TOTEM can be replaced by smaller adders, at the cost of introducing on-chip converters and paying an accuracy penality. The resulting architecture TOTEM++ is then presented. It is shown that the accuracy loss does not degrade the quality of the overall results when used in the context of neural network computation
Fast and Compact Controllers with Digital Neural Networks
1997-01-01
Abstract
This paper presents a hardware solution for the implementation of high-speed control systems based on a neural architecture that, by using a novel number representation, reduces significantly the silicon area required by the realization of the architecture as a digital chip. The neural architecture was originally implemented as the TOTEM neural chip. The new number representation is based on logarithms so that the costly multipliers of TOTEM can be replaced by smaller adders, at the cost of introducing on-chip converters and paying an accuracy penality. The resulting architecture TOTEM++ is then presented. It is shown that the accuracy loss does not degrade the quality of the overall results when used in the context of neural network computationI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
