A deeply-pipelined digital processor for the implementation of Multi-Layer Perceptrons is presented. It employs high-speed limited-precision integer arithmetic and allows good recognition performance in combination with a novel training algorithm. Internal dynamic RAM is provided for storage of the weights. The chip achieves a performance of 600 million multiply-and-accumulate operations per second and requires a silicon area of 70 mm2 in a 1.2-um CMOS technology

A Parallel Processor for Neural Networks

1995

Abstract

A deeply-pipelined digital processor for the implementation of Multi-Layer Perceptrons is presented. It employs high-speed limited-precision integer arithmetic and allows good recognition performance in combination with a novel training algorithm. Internal dynamic RAM is provided for storage of the weights. The chip achieves a performance of 600 million multiply-and-accumulate operations per second and requires a silicon area of 70 mm2 in a 1.2-um CMOS technology
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11582/1088
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