The Reactive Tabu Search (RTS) algorithm permits the training of neural networks with low number of bits per weight, low computational accuracy, no local minima "trapping", and limited sensitivity to the initial conditions. Two architectures for the implementation of Multi-Layer Perceptrons based directly on the properties of RTS are presented. They are characterized by high-speed integer computation, tunable precision, I/O balanced design, internal storage of the weights and compact processing units. TOTEM, a silicon implementation which uses only 8 bits per weight and 16 bits per input, is then presented. A triggering problem in High Energy Physics is used as a test-bed for the algorithm and the processor. The expected performance is briefly compared with those of two alternative processors
TOTEM: A Digital Processor for Neural Networks and Reactive Tabu Search
1994-01-01
Abstract
The Reactive Tabu Search (RTS) algorithm permits the training of neural networks with low number of bits per weight, low computational accuracy, no local minima "trapping", and limited sensitivity to the initial conditions. Two architectures for the implementation of Multi-Layer Perceptrons based directly on the properties of RTS are presented. They are characterized by high-speed integer computation, tunable precision, I/O balanced design, internal storage of the weights and compact processing units. TOTEM, a silicon implementation which uses only 8 bits per weight and 16 bits per input, is then presented. A triggering problem in High Energy Physics is used as a test-bed for the algorithm and the processor. The expected performance is briefly compared with those of two alternative processorsI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
