A low material budget silicon demonstrator has been tested by the SLIM5 collaboration with 12 GeV/c protons at the PS-T9 beam line at CERN. Two devices were placed inside a reference telescope and their characteristics were measured. The first was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130 nm CMOS technology, providing digital sparsified readout. The other one was a high resistivity double-sided silicon detector, with short strips at a 45∘ angle to the detector's edge, read out by the FSSR2 chip. In this paper we describe the main features of both sensors. The primary goal of the test was to measure the efficiency and the resolution of the DUTs under different conditions of threshold setting and incident angle of the impinging particles. The data-driven approach of the readout chips has been fully exploited by the DAQ system to take data with a track-based level-1 trigger provided by a pattern matching algorithm with very low latency.

The SLIM5 low mass silicon tracker demonstrator

Giacomini, Gabriele;Rachevskaia, Irina;Dalla Betta, Gian Franco;Soncini, Giovanni;
2010-01-01

Abstract

A low material budget silicon demonstrator has been tested by the SLIM5 collaboration with 12 GeV/c protons at the PS-T9 beam line at CERN. Two devices were placed inside a reference telescope and their characteristics were measured. The first was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130 nm CMOS technology, providing digital sparsified readout. The other one was a high resistivity double-sided silicon detector, with short strips at a 45∘ angle to the detector's edge, read out by the FSSR2 chip. In this paper we describe the main features of both sensors. The primary goal of the test was to measure the efficiency and the resolution of the DUTs under different conditions of threshold setting and incident angle of the impinging particles. The data-driven approach of the readout chips has been fully exploited by the DAQ system to take data with a track-based level-1 trigger provided by a pattern matching algorithm with very low latency.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11582/55789
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