The results obtained by the Slim5 collaboration on a low material budget tracking silicon demonstrator put on a 12 GeV/c proton test beam at CERN are reported. Inside a reference telescope, two different and innovative detectors were placed for careful tests. The first was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130 nm CMOS Technology, square pixels 50um wide, thinned down to 100um and equipped with a digital sparsified readout running up to 50 MHz. The other was a high resistivity double sided silicon detector, 200um thick, with short strips with 50um pitch at 45∘ angle to the detector's edge. The detectors were equipped with dedicated fast readout architectures performing on-chip data sparsification and providing the timing information for the hits. The criteria followed in the design of the pixel sensor and of the pixel readout architecture will be reviewed. Preliminary measurements of the pixel charge collection, track detection efficiencies and resolutions of pixel and strip sensors are discussed. The data driven architecture of the readout chips has been fully exploited in the test beam by a data acquisition system able to collect on electronic board up to 2.5 Million events per second before triggering. By using a dedicated Associative Memory board, we were able to perform a level 1 trigger system, with minimal latency, identifying cleanly tracks traversing the detectors. System architecture and main performances are shown.

Beam-test results of 4k pixel CMOS MAPS and high resistivity striplet detectors equipped with digital sparsified readout in the Slim5 low mass silicon demonstrator

Dalla Betta, Gian Franco;Soncini, Giovanni;Giacomini, Gabriele;Rachevskaia, Irina;
2010-01-01

Abstract

The results obtained by the Slim5 collaboration on a low material budget tracking silicon demonstrator put on a 12 GeV/c proton test beam at CERN are reported. Inside a reference telescope, two different and innovative detectors were placed for careful tests. The first was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130 nm CMOS Technology, square pixels 50um wide, thinned down to 100um and equipped with a digital sparsified readout running up to 50 MHz. The other was a high resistivity double sided silicon detector, 200um thick, with short strips with 50um pitch at 45∘ angle to the detector's edge. The detectors were equipped with dedicated fast readout architectures performing on-chip data sparsification and providing the timing information for the hits. The criteria followed in the design of the pixel sensor and of the pixel readout architecture will be reviewed. Preliminary measurements of the pixel charge collection, track detection efficiencies and resolutions of pixel and strip sensors are discussed. The data driven architecture of the readout chips has been fully exploited in the test beam by a data acquisition system able to collect on electronic board up to 2.5 Million events per second before triggering. By using a dedicated Associative Memory board, we were able to perform a level 1 trigger system, with minimal latency, identifying cleanly tracks traversing the detectors. System architecture and main performances are shown.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11582/55382
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