Improvements achieved in the fabrication of JFET transistors on high-resistivity silicon by means of TCAD simulations

The TCAD simulator is an indispensable tool both for the design of new devices based on semiconductor technology as well as for a thorough understanding of the device functioning. This paper reports the improvements achieved in the characteristics of JFET transistors built on high-resistivity silicon by exploiting the information extracted from process and device simulations to tune the fabrication technology. The first part of the report gives some examples of simulation outcomes already implemented in the fabrication process and the relative impact on the device performance, whereas the second presents possible improvements to be applied in the following productions to render the device more robust